Sound Master (Canopus)

Hi-Fi specification C bus A / D, D / A conversion board with DMA function and visual waveform
A set of handling software.Board has 2 channels of 20kHz 7th order low pass
Filter + 2 channels simultaneous sample hold + 16 bits A / D, D / A.
Two 8-deep dip switches, one two-jumper switch, three on the board
There are 2 jumper switches.

Input / output code: 2's complement binary (16 bits)
Input / output voltage: -3V to + 3V
Number of input / output channels: 2 channels
Cross-channel crosstalk: -60 dB or more (at maximum output)
Distortion rate: 0.03% or less
Sampling clock: 32 kHz, 44.1 kHz, 48 kHz, external
Filter: 20 kHz, 7th-order low pass filter
DMA channel: one of Ch 0, 2 and 3
Power consumption: +5 V = 500 mA MAX, ± 12 V = 70 mA MAX

The parts on the back of the board are those viewed from the back (7) (6) (5) (4) (4) (3) (2) (1)
If you
　(1) Volume for Rch.The sound of the right channel becomes smaller counterclockwise.
　(2) Volume for Lch.The sound of the left channel becomes smaller counterclockwise.
　(3) Rch IN. Right channel input pin jack (red).
　(4) Lch IN. Pin jack for left channel input (white).
　(5) Rch OUT. Right channel output pin jack (red).
　(6) Lch OUT. Pin jack for left channel output (white).
　(7) EXT CLK. External clock input connector (3 pins).From the left + 5V,
　　　　　　　In order of input (TTL level), digital ground.
(3) to (6) can be connected directly to the stereo amplifier REC OUT / PLAY terminal.
Do not connect to the speaker output terminal (voltage relationship).

There are three crystal oscillators on the board, but I saw the board with the card edge on the left
The top one (for 4.096 MHz, 32 KHz) is interchangeable.Oscillation frequency 1/128
Is the sampling frequency.

・ 8 series jumper switch DS1, DS2: I / O port address setting
　The following I / O port addresses are used by this board:
　The following is the order of port name, read / write, I / O port address
　CONT ■ light ■ xxx0 or xxx8
　ADST light ■ xxx 1 or xxx 9
　WLBD ■ Light ■ xxx2 or xxxA
　WHBD ■ Light ■ xxx 3 or xxx B
　DMFQ ■ Light ■ xxx 4 or xxx C
　MODE ■ light ■ xxx7 or xxxF
　ROVRN ■ lead ■ xxx 0 or xxx 8
　STAT ■ lead ■ xxx1 or xxx9
　RLBD ■ lead ■ xxx2 or xxxA
　RHBD ■ lead ■ xxx3 or xxxB
　Set xxx part with dip switch.Upper 8 bits to DS1, lower 8 bits
　To DS2 and dip each bit from top to bottom
　Corresponds to 8, 7, 6, and so on.
　　Example 1) When setting to 00D0h.Order of DS1 DS2:
　　OFF-OFF-OFF-OFF-OFF-OFF-OFF-OFF-ON-ON-OFF-ON-OFF-OFF-OFF-OFF-OFF-OFF
　　Example 2) When setting to 02D0h
　　OFF-OFF-OFF-OFF-OFF-OFF-ON-OFF ON-ON-OFF-ON-OFF-OFF-OFF-OFF-OFF

・ 2 jumper switch JP1: Whether word transfer is possible
　Short ■ word transfer permission
　Open ■ Word transfer not possible
　Word for PC-9801 / E / F / M / VM / VF / UV / CV / UR / UF / LV / N / NV / NS, FC-9801 / V
　Transfer impossible.

· Three jumper switches JP2 and JP3: Built-in filter ON / OFF. JP2 is the right channel,
　JP3 is the left channel setting.
　○ 2 shorts on the mark side ■ Built-in filter ON
　○ marked and opposite 2 shorts ■ Built-in filter OFF

・ A / D conversion function: Fixed bipolar input of -3V to + 3V.This A / D conversion range is 16
　Divided into 1/65536 by bit binary data.
　FFFFh-3V
　F 000 h ■-0.375 V
　9000h ■ -2.625V
　8000 h 0 V
　7000h ■ 2.625V
　1000h ■ 0.375V
　0000h ■ 2.999V
・ D / A conversion function: Because digital data is 16-bit binary data
　Divide the signal into 1/65536 and output the analog signal (fixed -3V to + 3V bipolar output).
　The representation format of digital data is 2's complement binary (2's complement binary).
　Below, the order of the scale 2's complement code (FS means full scale)
　+ FS-1 LSB 0111 1111 1111 1111
　+7/8 FS 0111 0000 0000 0000
　+3/4 FS 0110 0000 0000 0000
　+5/8 FS 0101 0000 0000 0000
　+ 1/2 FS 0100 0000 0000 0000
　+3/8 FS 0011 0000 0000 0000
　+1/4 FS 0010 0000 0000 0000
　+1/8 FS 0001 0000 0000 0000
　0 + 1 LSB 0000 0000 0000 0001
　0 ■ 0000 0000 0000 0000
　0-1 LSB 1111 1111 1111 1111
　-1/8 FS 1111 0000 0000 0000
　-1/4 FS 1110 0000 0000 0000
　-3/8 FS 1 1 1 0000 0000 0000
　-1/2 FS-1100 0000 0000 0000
　-5/8 FS 1011 0000 0000 0000
　-3/4 FS-1010 0000 0000 0000
　-7/8 FS ■ 1001 0000 0000 0000
　-FS 1000 0000 0000 0000
-------------------------------------------------------- -----------
I / O port
■ Light port
・ CONT
　WR0 (I / O port address + 0) 0-0-0-0- 0-DMA-OSC-OVENRES
　DMA: Set 1 when performing DMA transfer.Data transfer by I / O instruction
　　　If you want to set 0.
　OSC: Set 1 when operating internal / external clock, stop at 0.
　OVRNRES: When ADOVRN or DAOVRN of read port ROVRN becomes 1,
　　　　　 Set this bit to 1 to reset.
・ ADST
　WR1 (I / O port address + 1) AD conversion start
　A / D conversion is performed once when all bits of this port are set to 0.
・ WLBD
　WR2 (I / O port address + 2) D7-D6-D5-D4-D3-D2-D1-D0
　Sets the lower 8 bits of data for D / A conversion.Word data in WLBD
If (16 bits) is set, D / A conversion data can be set at once.　
· WHBD
　WR3 (I / O port address + 3) D15-D14-D13-D12-D11-D10-D9-D8
　Set the upper 8 bits of data for D / A conversion.
・ DMFQ
　WR 4 (I / O port address + 4) 0-X 20 VS MP-CK 1-CK 0-DMACH-DISTC-ST-WT
　X2OVSMP: Set 1 when performing A / D-D / A conversion with 2 × oversampling.
　However, this bit is limited to the use of only one of Lch and Rch.
　CK1, CK0: Following, CK1 CK2 Frequency in order
　　0 * 0 * 32 kHz (expansion)
　　0 1 1 44.1 kHz
　　1 ■ 0 ■ 48kHz
　　1 ■ 1 ■ External clock
　　The crystal oscillator for expansion should be twice the sampling frequency.Also outside
　　Make the clock 8 times the sampling frequency.
　DMA channel 0: DMA channels 0 and 1 and DMA channels 2 and 3 selected.
　DISTC: Normally 0, 1 not complete with terminal count (DMA controller
　　　　 This bit when the 8237A is in auto-initialization mode
　　　　 If you set to 1, DMA transfer will continue without termination for a long time).
　ST, WT (during DMA transfer): The following order of ST WT contents
　　0 ■ 0 ■ byte transfer
　　0 1 1 Word transfer
　　1 • 0 • short transfer (transfer only upper 8 bits)
　　1 1 1 prohibited
　　When DMA transfer is not performed, both ST and WT are set to 0.
・ MODE
　WR7 (I / O port address + 7) INIT-0-0-ADDA-0-RL
       Note: ADDA is AD = 0, DA = 1
　Reset all ports with INIT: 1 (port MODED also reset).this
　　　　Simultaneous setting of a bit and other bits is not possible.
　ADDA: 0 in A / D conversion mode, 1 in D / A conversion mode.
　L, R: Set 1 to the channel you want to use.When both L and R channels are used
　　　　Set 1 together.
　　※ In clock synchronous mode and DMA transfer mode of A / D and D / A conversion,
　　　When both L and R channels are selected, data read in the order of L-> R
　　　/ Do the light.
■ Lead port
・ ROVRN
　RD0 (I / O port address + 0) XXX-DAOVRN-X-DMA-OSC-ADOVRN
　DAOVRN: While the DEMP flag of the read port STAT is 1 and data is accepted
　　　　　When the conversion clock is output (D / A converter changes output
　　　　　Is set to 1 (data written by software)
　　　　　For checking the legitimacy of).This bit is once set to 1
　　　　　Set the OVRNRES of the light port CONT to 1
　　　　　Holds 1 until the system is reset.
　DMA: 1 is set during DMA transfer.To DMA controller
　　　　It is reset to 0 when the programmed number of bytes is transferred.
　OSC: 1 is set when the transmitter is operating, reset to 0 when stopped
　　　 It is done.
　ADOVRN: The DRDY flag of the read port STAT remains 1 and the next conversion is completed,
　　　　　1 if the previous data is lost without being read
　　　　　Checking the validity of the data written by the software to be set
　　　　　for).
　　　　　Once this bit is set to 1, OVRNRES for light port CONT
　　　　　Holds 1 until it is set to 1 or the system is reset.
STAT
　RD1 (I / O port address + 1) DEMP-XXXXX-EOC-DRDY
　DEMP: 1 is set when writable, and data is written
　　　　It becomes 0.
　EOC: A / D converter is converting 1 being set, ending 0.
　DRDY: A / D converter finishes conversion and new data can be read
　　　　When it becomes 1, 1 is set, and when it is read out 0.
・ RLBD
　RD2 (I / O port address + 2) D7-D6-D6-D4-D3-D2-D1-D0
　The lower 8 bits of data of A / D conversion result are set.Note that port RLBD
　Read word data (16 bits) from A / D conversion data at once
　It can be done.
・ RHBD
　RD3 (I / O port address + 3) D15-D14-D13-D12-D11-D10-D9-D8
　The upper 8 bits of data of A / D conversion result are set.

If you use the DMA function, how to use the DMA controller 8237A
To understand.